Peel1/2xx series:PEEL153 PEEL173 PEEL153P PEEL173P PEEL253 PEEL273 ...
Peel16xx series:PEEL16CV8 PEEL16V8 ...
Peel18xx series:PEEL18CV8 PEEL18CV8Z PEEL18LV8Z ...
Peel20xx series:PEEL20CG10 PEEL20CG10A PEEL20V8 ...
Peel22xx series:PEEL22CV10 PEEL22CV8 PEEL22CV10 PEEL22CV10A PEEL22CV10A PEEL22CV10A PEEL22CV10AZ PEEL22CV10AZ PEEL22CV10AZ PEEL22LV10AZ PEEL22LV10AZ PEEL22LV10AZ ...
Over the last few years a great deal of attention has been focused on higher pin count Complex PLDs (CPLDs). When first introduced, these newer and larger PLDs were predicted to totally replace Simple PLDs (SPLDs) such as PAL, GAL and PEEL? Devices. While CPLDs have their merits, they have not eliminated the demand for SPLDs. Why the continued popularity of SPLDs? As PACE Technologies PLD Market analyst, Ronnie Rohleder stated in her Electronic Buyers News column, ˇ°...they're fast, cheap and ease-to-use... no sophisticated development system is required, and there's a wide range of architectures...ˇ± The most flexible architectures among SPLDs are provided by PEEL? Devices from ICT See Figure 1. PEEL? Products from ICT PEEL? Devices are PAL, GAL and EPLD replacements, many of which offer enhanced architectures allowing more logic to be packed into every part. They're ideal for designers who have pushed ordinary PAL/GAL architectures to the limits and need more capability without the cost, complexity and learning curve associated with most CPLDs. PEEL? Devices are offered in a wide range of speed and power options. Development support for PEEL? Devices is provided by ICT and popular third party development tool and programmer manufacturers, such as BP Microsystems. ICT offers the powerful and easy-to-use PLACE Development Software (free to qualified PLD Designers) complete with architectural editor, logic compiler and waveform simulator.
The ICT PEEL Arrays are large PLAs which include logic macrocells with flip-flops and feedback to the logic planes. Figure below shows a programmable AND-plane that feeds a programmable OR-plane. The outputs of the OR-plane are divided into groups of four and each group gives input to any of the logic cells. The logic cells provide registers for the sum terms and can feed-back the sum terms to the AND-plane. Because of PLA-like structure, logic capacity of PEEL Arrays is somewhat difficult to measure compared to the CPLDs. PEEL Arrays offer relatively few I/O pins, with the largest part being offered in a 40 pin package. The logic cell in the PEEL Arrays consists of a flip-flop, configurable as D, T, or JK, and two multiplexers. The multiplexers produce output of the logic cell and provide a registered or combinational output. The logic cell outputs connect to an I/O pin.
PEEL? Device Types There are two basic types of PEEL? Device:
direct replacements and superset replacements. See Table 1. Direct replacement PEEL? Devices include the PEEL? 22CV10A, 22CV10AZ. These devices are JEDEC file and function compatible with industry-standard architectures. Superset replacement PEEL? Devices include the PEEL? 18CV8, 18CV8Z, 18LV8Z, 22CV10A+, 22CV10AZ+, and 22LV10AZ. These devices provide additional architecture features, beyond those of ordinary SPLDs, such as the 12-configuration macrocell. Architectural Enhancements Designing with PEEL? Devices is much like designing with other 20 or 24-pin SPLDs. However, superset PEEL? Devices give designers greater flexibility with additional inputs, product terms and macrocell configurations. An example of this is shown in Table 2, which compares a standard 16V8/22V10 architecture with an 18CV8/ 22CV10A enhanced architecture. The following information describes some of the design benefits of PEEL? Devices enhanced architectures. Figure 1 PEEL? Devices offer flexible architectures at attractive speeds and prices. Independent Output Enables Each I/O has independent programmable output enables for both combinatorial or registered outputs. The output enables are helpful for bus interfacing as well as ˇ°wire-ORingˇ± of signals. Each I/O can be enabled or disabled via individual product terms, even on registered outputs where most standard PLDs offer only a single output enable control pin. Global Preset and Clear The PEEL? 18CV8, and 22CV10AZ have a synchronous preset (SP) and an asynchronous clear (AC) product term that control all the registers. Although these functions are fairly straightforward, there are some unique ways to take advantage of them, especially for counters and state machines. An example is shown in the 8-bit Counter with Function Controls design in application note AN-1A in this data book.
All of ICT's superset SPLDs have a twelve-configuration
macrocell as shown in Figure 2. Macrocell configuration
numbers 3, 4, 9, and 10 (shaded in Figure 2) are the four
macrocell configurations most similar to the standard
SPLDs such as the 16V8 and 22V10. The additional eight
macrocell configurations (1, 2, 5, 6, 7, 8, 11, and 12) can be
used for a variety of logic functions not possible with ordinary SPLDs. These functions include:
l Bi-Directional Registered I/O
l Buried Combinational Feed back
l Buried Combinational Feedback with Register
l Buried Register with Combinatorial Output
The flexible output enable and register preset/clear controls
can be used together with the extra macrocell configurations to implement a wide range of designs that will not fit
into other devices. See AN-1A for design tricks and techniques that show details of how to use the enhanced
PEEL? Device architecture for real applications.
Quick PEEL? Device Cross Reference
P E E L 2 2 C V 8
P3C18V8 PEEL 18LV8Z
Vantis ( AMD) ICT